Modern integrated circuits commonly come in the form of chips. The integrated circuits within a chip communicate with the world outside the chip through metalization layers on the outside of the chip known as signal pads. For communication from within the chip to the world outside, "driver circuits" drive signals or data through the signal pads on the exterior of the chip. The signal pads of various chips are connected together by signal lines thereby allowing communications between different chips.
The signal pads on a chip are then connected to the packaging of the chip which is then connected to a signal trace on a printed circuit board which runs to another integrated circuit chip or other similar device. The electrical connection from the signal pad through the packaging of the chip to the transmission line contains parasitic resistance, inductance, and capacitance which interferes with the transmission of the signal from the signal pad. The printed circuit board signal trace itself also contains transmission line characteristics which include resistance, capacitance, and inductance which also interfere with the quality of the transmitters of the signal from the signal pad. All of the foregoing add to the load which must be driven by the driver circuit.
Because of the parasitic resistance, inductance, and capacitance which is present on chip to chip signal interconnections, the driver circuits that drive those signal interconnections are preferably designed to avoid excessive voltage swings when switching occurs (particularly for high speed or low power I/O). Excessive voltage swings are known as ringing. Ringing must be avoided while still switching as fast as possible to meet the high speed performance requirements of modern integrated circuits.
In the past, CMOS drivers have utilized NMOS (and/or PMOS) FET's to drive the signal pad to a voltage level based on a clocked or static input to the driver input. The drive NMOS FET's are turned on or off based on the inputs from inside the chip and stay in that state, regardless of the state of the transmission line being driven.
Due to process variations inherent in the manufacturing process of integrated circuits, different integrated circuits intended to perform the same function can be classified as "slow", "nominal," or "fast". During the manufacturing process for integrated circuits, variations in certain parameters occur. For example, the doping level, the length of channels in FET's, the thickness of the gate oxide for transistors, the diffusion resistance and other characteristics of integrated circuits vary during the manufacturing process. In other words, two supposedly identical integrated circuits can vary in all of those characteristics. As those characteristics approach the fast case, the resistance of many components within a chip is decreased. In the opposite extreme, as those characteristics stray further and further from the ideal case, the performance of the chip is degraded, specifically, the resistance of the many components within the chip is increased, and that situation will be referred to as the slow case.
Also, variations in voltage and temperature can cause a single chip to behave as if it is fast or slow. For example, when the temperature of an integrated circuit approaches its maximum operating temperature, the resistance of FET's in the integrated circuit increases. It is desirable to have a single driver circuit which can operate effectively and still avoid excessive voltage swings regardless of whether the integrated circuit is fast or slow.
In prior systems the size of the FET's driving the signal interconnects have been limited in size in order to minimize excessive voltage overshoot and undershoot when the process parameters are such that the NMOS FET's own impedance is at a minimum and the interconnects impedance is at its maximum. However, this approach has limited the speed of switching when variations in the process parameters have moved these impedances to the opposite case.
This approach has caused an additional problem in system timing. It has increased the uncertainty of placement of the switching transition in time. This has limited the system frequency and causes a degradation in performance.
One approach known in the prior art to address this problem is to provide a programmable output driver stage in a CMOS output driver. One such circuit is illustrated in FIG. 1. The figure shows programmable current sources 21 (which serves to control the impedance of FETs 12 and 13) and two output driver stage 22. The CMOS output stage 22 drives a capacitively terminated transmission line 17. The transmission line has a characteristic impedance of Zo. Programmable current source 21 determines a composite source impedance for the CMOS output driver stage. That composite source impedance can be separated into a value Rsc (the source resistance while charging) and a value Rsd (the source resistance while discharging). Generally speaking, it is desirable that Rsc and Rsd be equal to each other and to the characteristic impedance Zo of the transmission line 17, although one can imagine that there might be special circumstances that would require them to be different.
Note the capacitive load 18 at the other end of transmission line 17. The system may employ a well understood technique of doubling the output voltage by using reflected power from the reactive (and non power dissipative) discontinuity (capacitive load 18) at the terminus of the transmission line 17. It is the desire to achieve the full doubling, but without added overshoot (Zo too low plus the evil of multiple reflections) or excessive rise time (Zo too high and the attendant multiple reflections), that leads to extra concern about the source impedance of the output driver stages 22 and 23. Note that when the load is reactive, the power that is launched by charging through Rsc is: transmitted out through Zo, reflected (and the voltage at the load is doubled); transmitted back through Zo; and is then absorbed by discharging, without re-reflection, by a still on Rsc. A similar sequence of events occurs for discharging involving Rsd. (All provided, of course, that Rsc=Zo=Rsd). Yet even in a situation where there is a resistive termination with the expectation of genuine power transfer to the load without reflection, it is still important to control the source impedance of the output driver stages.
To appreciate the operation of the CMOS device, consider output driver stage 22, which includes four CMOS devices 12, 13, 14, and 15 connected as shown. Devices 14 and 15 act as switches to respectively pull-up (charge to DVDD) and pull-down (discharge to DGND) on the output terminal 16 that drives the transmission line 17 whose Zo is to be matched by Rsc (during pull-up) and by Rsd (during pull-down). It will be understood that switching devices 14 and 15 are driven on and off in suitable alternation in accordance with the desired output waveform, and that although both devices 14 and 15 may be off to tri-state output terminal 16, both devices will never be on at the same time. In this regard, driver circuits 32 and 34 are provided to turn the switching devices 14 and 15 ON and OFF. Generally, and as is known, one driver circuit 32 operates to control the FET 14 to drive the output signal from a low to high value, while a second driver circuit 34 operates to control the FET 15 to drive the output signal from a high to low value.
Device 13 acts as a resistance of programmable value to combine with the very low on resistance of device 14 to produce Rsc. Similarly, device 12 acts as a resistance of programmable value to combine with the relatively low on resistance of device 15 to produce Rsd. The resistance of device 13 is controlled by the value of the voltage PGATE 20, while in similar fashion the resistance of device 12 is determined by the value of the voltage NGATE 19. Assuming now that the P-type device 13 and N-type device 12 have generally equal transconductance, the signals NGATE 19 and PGATE 20 are controlled such that they (1) can be externally varied to adjust Rsc and Rsd over a suitably wide range of Zo despite process variations; (2) vary together such that as NGATE increases from DGND toward DVDD, PGATE decreases correspondingly from DVDD toward DGND; and (3) automatically adjust to compensate for the effects of temperature. One manner and circuit for achieving these objectives is described in U.S. Pat. No. 5,581,197, assigned to the assignee of the present invention, and is hereby incorporated by reference in its entirety. While the circuitry described above effectively varies the output impedance over process and temperature variations, it has been found that the performance of the circuit can be significantly (adversely) affected by even relatively small amounts of noise. Accordingly, it is desirable to provide an improved output driver stage that effectively varies its output impedance over process, voltage, and temperature (PVT), and is less susceptible to the adverse effects of noise. More particularly, it is desirable to provide an improved output driver stage that can effectively vary its output impedance to precisely match board trace impedance, as that impedance changes over process, temperature, and voltage.